Memory cell arrangement and method for its fabricating it

ABSTRACT

The present invention relates to a memory cell arrangement and a fabrication method for this memory cell arrangement. In this case, the memory cells ( 15   a,    15   b,    15   c ) arranged regularly on a semiconductor wafer each have a trench capacitor ( 20   a,    20   b,    20   c ) formed in the semiconductor substrate ( 10 ), and a selection transistor ( 30   a,    30   b,    30   c ) formed above the trench capacitor ( 20   a,    20   b,    20   c ), and also a self-aligned selection transistor ( 30   a,    30   b )—memory trench contact ( 40   a,    40   b )—trench insulation ( 52 ) arrangement.

[0001] The invention relates to a memory arrangement having amultiplicity of memory cells which are arranged regularly in a matrixform and each have a storage capacitor and a selection transistor, whichare isolated from one another in the bit line direction by self-alignedinsulation structures arranged orthogonally with respect thereto, andalso a fabrication method for such a memory arrangement.

[0002] A dynamic random access memory (DRAM) contains a multiplicity ofmemory cells which are formed regularly in the form of a matrix on asemiconductor wafer. Each of these memory cells generally comprises astorage capacitor and a selection transistor. During a read or writeoperation, the storage capacitor is charged or discharged with anelectric charge, corresponding to the respective data unit (bit), viathe selection transistor. For this purpose, the memory cell is addressedwith the aid of a bit line and a word line, which are arranged in rowform and column form and generally run perpendicularly to one another.

[0003] The continuous trend for increasing the packing density ofintegrated circuits (ICs) especially including dynamic memory ICs, meansthat the substrate area available for an individual memory cell isreduced, which affects the electrically active elements of the memorycell (transistor, contacts, storage capacitance) as well as theinsulation structures (field insulation). For trench memory cells, thetrench diameter of the memory trench is reduced and so the capacitanceof said trench is reduced as well, as a result of which the risk of readerrors is increased. In the case of the insulation structures (fieldinsulation), the insulation distance is reduced, thereby reducing thesecurity of the insulation of adjacent elements. Both of these must beprevented by suitable measures.

[0004] One possible solution to these problems is to effect a suitablearrangement of the elements of the memory cells. In this arrangement, anepitaxial semiconductor layer is applied above the trench capacitors andthe selection transistors are formed in this semiconductor layer abovethe respective trench capacitor. Since each of these two functionalelements is advantageously arranged, stacked, in a different plane ofthe active silicon, the memory cell area does not have to be dividedproportionally between these elements and can thus be configuredminimally overall. What is difficult in the case of this arrangement,however, is the fabrication of the so-called strap contacts, thecontact-connection of the two memory cell component parts, since thesestrap contacts within the semiconductor layer have a relatively highaspect ratio.

[0005] DE 199 41 148 A1 describes such a method for fabricating contactsbetween a trench capacitor and a selection transistor formed above thetrench capacitor.

[0006] The object of the present invention is to provide a memory cellarrangement having memory cells in which a simple and space-savingcontact-connection of selection transistor and storage capacitor, whichare arranged one above the other, is ensured, and also to provide amethod for fabricating such a memory cell arrangement.

[0007] This object is achieved by means of a method for fabricating amemory cell arrangement in accordance with claim 1 and a memory cellarrangement in accordance with claim 10. Preferred developments arespecified in the dependent claims.

[0008] According to the invention, a contact opening is formed in thesemiconductor layer in the interspace between two memory cells that areadjacent in the bit line direction, which contact opening reaches as faras the inner electrodes of the respective trench capacitors and, afterthe fabrication of a collar insulator layer on the uncovered sidewallsof the contact opening, is filled with a conductive material in such away that the inner electrodes of the trench capacitors are electricallyconductively connected to the selection transistors arranged above them.Afterward, in the contact opening, an insulation opening is produced asfar as a level below the upper edge of the storage capacitors and isfilled with an insulator, as a result of which the electricallyconductive layer in the contact opening is subdivided into two partialregions that are insulated from one another, so that each of the partialregions forms a strap contact which electrically connects the innerelectrode of the trench capacitor to the selection transistor of therespective memory cell.

[0009] What is significantly advantageous in the case of the methodaccording to the invention or the structure according to the inventionis that the strap contacts, which are initially fabricated as onecontact point, are only separated by the formation of the trenchinsulation in this contact point. The wider contact hole of the contactpoint has a significantly more favorable aspect ratio for processingthan two separate contact holes, as a result of which the processcomplexity is reduced. Furthermore, very narrow strap contacts and strapinsulations can be fabricated by the method according to the inventionin comparison with the conventional methods.

[0010] Since the formation and the filling of the contact hole iseffected in a self-aligned manner with respect to the word lines or theinsulation encapsulations of the word lines of the two memory cells,complicated method steps can be obviated.

[0011] In accordance with an advantageous embodiment, an opening with afunnel-shaped profile is produced by anisotropic etching of a spacerlayer deposited on the electrically conductive layer in the contactopening, the width of the opening decreasing with depth. In thesubsequent process steps, the patterned spacer layer serves as a maskfor the fabrication and filling of the insulation opening in theelectrically conductive layers of the contact opening. This obviates aphotolithographic mask step for fabricating and filling the insulationopening. The thickness of the spacer layer, which can be set veryprecisely, determines very exactly the width of the etched opening andthe width of the insulation opening produced underneath. At the sametime, this also enables the width of the strap contacts to be determinedvery precisely. In particular, however, this method enables insulationopenings whose width is narrower than the minimum possible lithographicweb width.

[0012] In an advantageous embodiment of the invention, a thin collarinsulator layer is produced at the uncovered sidewalls of thesemiconductor layer in the contact opening. This insulator layer servesas insulation of the electrically conductive layer in the contactopening with respect to the semiconductor layer. This avoids leakagecurrents which could discharge the trench capacitor.

[0013] In an advantageous embodiment of the invention, the thin collarinsulator layer is produced in the contact opening with the aid of aninsulation step. This method has the advantage that a uniform insulatorlayer can thus be produced very simply, this being difficult to do withthe layer deposition method usually used in particular at thesteep-edged sidewalls of the semiconductor layer.

[0014] The invention is explained in more detail with reference to theaccompanying drawings.

[0015] In the figures:

[0016]FIGS. 1A to 1L show a process sequence according to the inventionfor fabricating a self-aligned strap contact-trench insulationarrangement in a memory cell arrangement according to the invention;

[0017]FIG. 2 shows a cross section through a region of a memory cellarrangement according to the invention which has been produced by meansof the process sequence illustrated in FIGS. 1A to 1F; and

[0018]FIG. 3 shows a plan view of a memory cell arrangement according tothe invention.

[0019] The process sequence according to the invention is illustratedusing the example of a self-aligned strap contact-trench insulationarrangement of two adjacent memory cells in a dynamic random accessmemory (DRAM). However, the process sequence according to the inventioncan also be used to form contacts between component parts that arearranged offset in other known semiconductor components.

[0020]FIGS. 1A to 1L each show a cross section through a semiconductorwafer with three memory cells 15 a, 15 b, 15 c after different processsteps, three trench capacitors 20 a, 20 b, 20 c being formed in thesemiconductor substrate 10 in the lower part of FIG. 1A. Each of thesetrench capacitors 20 a, 20 b, 20 c comprises an inner electrode 21,which is formed as a trench filled with, preferably, doped polysilicon,an insulator layer 22 surrounding the trench filling 21, and aninsulation covering layer 23 covering the trench filling 21. As a resultof the high integration density of the memory cell arrangement, thetrench capacitors 20 a, 20 b, 20 c are arranged very close together, andthey are separated from one another in the bit line direction byrelatively thin webs 11 in the semiconductor substrate 10. The outerelectrode of each of the trench capacitors 20 a, 20 b, 20 c forms anelectrically conductive region (not illustrated here) within thesemiconductor substrate 10 which surrounds the trench capacitor 20 a, 20b, 20 c preferably at least in the lower region.

[0021] A semiconductor layer 12, which is preferably formed as anepitaxially grown monocrystalline silicon layer, is applied on theinsulation covering layer 23 of the trench capacitors 20 a, 20 b, 20 c.Between the rows of memory cells 15 running in the bit line direction asshown by the plan view in FIG. 3, insulation trenches 53 from previousprocess steps are formed within the semiconductor layer 12, whichpreferably extend as far as the substrate surface. These insulationtrenches 53 are filled with an insulator material and form a fieldinsulation in the word line direction between the memory cells 15.

[0022] A selection transistor 30 a, 30 b, 30 c is respectively formedabove each of the trench capacitors 20 a, 20 b, 20 c in thesemiconductor layer 12. For this purpose, electrically conductiveregions 31 a, 31 b are formed in the upper region of the semiconductorlayer 12 essentially above the webs 11 of the semiconductor substrate 10which separate the trench capacitors 20 a, 20 b, 20 c, said electricallyconductive regions being separated by a respective channel region 32situated essentially above the respective trench capacitor 20 a, 20 b,20 c.

[0023] An electrically conductive layer 37 is in turn formed above eachchannel region 32, which layer forms the gate electrode of therespective selection transistor 30 a, 30 b, 30 c or the word line 33 a,33 b, 33 c and is electrically insulated from the channel region 32 andthe electrically conductive regions 31 a, 31 b within the semiconductorlayer 12 by a thin gate insulator layer (not illustrated here). Eachword line 33 a, 33 b, 33 c is electrically insulated laterally andtoward the top by an insulation encapsulation 34.

[0024] The regions between the insulation encapsulations 34 of the wordlines 33 a, 33 b, 33 c are essentially completely filled with a firstinsulator layer 13 in the first process stage shown in FIG. 1A. In theexemplary embodiment illustrated here, the two memory cells 15 b, 15 care connected to a bit line 35 via a common bit line contact 35 a.

[0025] A strap contact-trench insulation arrangement according to theinvention is fabricated between the two memory cells 15 a, 15 b by meansof the process steps explained below. In order to protect the bit linecontact 35 a, between the memory cells 15 b, 15 c, as is shown in FIG.1A, a protective layer 14 is applied on the insulator layer 13 and theinsulation encapsulations 34 of the word lines 33 a, 33 b, 33 c, whichprotective layer is patterned with the aid of a photolithographic stepin such a way that a strip-type structure is formed in the direction ofthe word lines 33 a, 33 b, 33 c, the layer strips covering the regionbetween the word lines 33 b, 33 c, while the region between the wordlines 33 a, 33 b is uncovered. The strip-type protective layer 14preferably has a high resistance with respect to the eroding methods ofthe subsequent process steps and serves as a selection mask during thefabrication of the strap contact-trench insulation arrangement accordingto the invention.

[0026] In a further process step, an opening 44 b is fabricated betweenthe memory cells 15 a, 15 b, which opening is referred to as a spacertrench hereinafter. As is shown in FIG. 1B, for this purpose theinsulator layer 13 is removed between the insulation encapsulations 34of the word lines 33 a, 33 b down to the semiconductor layer 12,preferably by means of an anisotropic etching method. Since theinterspace between the memory cells 15 b, 15 c is covered by thestrip-type protective layer 14, this process step is advantageouslyeffected without a further lithographic mask step, the strip-typeprotective layer 14 and the insulation encapsulations 34 of the wordlines 33 a, 33 b serving as an etching mask. In this case, as is shownin FIG. 3, spacer trenches 44 b running along the insulationencapsulations 34 of the word lines 33 a, 33 b are formed.

[0027] In the next process step, in the spacer trench 44 b, in a regionbetween the insulation encapsulations 34 of the word lines 33 a, 33 band the insulation structures in the bit line direction 53, a contactopening 44 a is then formed in the semiconductor layer 12 down to theinsulation covering layers 23 of the polycrystalline trench filling 21of the trench capacitors 20 a, 20 b. For this purpose, as shown in FIG.1C, the semiconductor layer 12 is etched selectively, preferably bymeans of an anisotropic etching method, the strip-type protective layer14, the insulation encapsulations 34 of the word lines 33 a, 33 b andthe insulation structures 53 formed in the semiconductor layer 12serving as etching mask during this etching step.

[0028]FIG. 1D shows a further process step, which produces the access tothe polycrystalline trench fillings 21 of the trench capacitors 20 a, 20b, in the contract opening 44 a. For this purpose, the uncovered partialregions of the insulation encapsulations 22 and of the insulationcovering layers 23 of the trench capacitors 20 a, 20 b are removed bymeans of a selective etching method, thereby uncovering the underlyingpartial regions of the respective trench filling 21.

[0029] In FIG. 1E, a thin insulator layer 43 is formed in the contactopening 44 a on the uncovered sidewalls of the semiconductor layer 12,the electrically conductive regions 31 b of the selection transistors 30a, 30 b, the polycrystalline trench filling 21 of the trench capacitors20 a, 20 b and also the upper uncovered regions of the web 11 of thesemiconductor substrate 10 between the trench capacitors 20 a, 20 b,which insulator layer is preferably fabricated by means of CVDdeposition (chemical vapor deposition) or oxidation.

[0030] In FIG. 1F, the thin insulator layer 43 produced in the contactopening 44 a is removed again by means of an anisotropic etching step,except for the regions on the steep sidewalls of the contact opening 44a. The remaining regions of the insulator layer 43 serve, in the memorycell arrangement, as an electrical insulation of the subsequently formedstrap contacts 40 a, 40 b from the semiconductor layer 12 and thusreduces leakage currents which [lacuna] to the discharge of the trenchcapacitors 20 a, 20 b and to the shortening of the retention time, themaximum period of time after which the charge stored in a memory cell 15must be refreshed.

[0031] In the subsequent step, as shown in FIG. 1G, a first electricallyconductive layer 41 a is deposited in the contact opening 44 a, whichlayer is preferably composed of doped polysilicon and is referred to asfirst contact layer hereinafter.

[0032] For the contact-connection of the selection transistors 30 a, 30b, in the subsequent process step, the partial regions of the insulatorlayer 43 covering the electrically conductive regions 31 b of theselection transistors 30 a, 30 b are removed. For this purpose, firstlythe first contact layer 41 a is removed again as far as a level justbelow the surface of the semiconductor layer 12, by means of aplanarizing etching method. Afterward, the uncovered partial regions ofthe insulator layer 43 are removed with the aid of an isotropic etchingmethod until the electrically conductive regions 31 b of the selectiontransistors 30 a, 30 b are uncovered. In this case, as illustrated inFIG. 1H, the first contact layer 41 a in the contact opening 44 a, theinsulation encapsulations 34 of the word lines 33 a, 33 b and thestrip-type protective layer 14 serve as etching mask.

[0033] As shown in FIG. 1I, in the subsequent process step forcontact-connection of the selection transistors 30 a, 30 b, a secondelectrically conductive layer 41 b which is preferably composed of dopedpolysilicon and is referred to as second contact layer hereinafter isdeposited onto the first contact layer 41 a in the contact opening 44 aas far as a level preferably just above the electrically conductiveregions 31 b of the selection transistors 30 a, 30 b, so that thecontact block 40 comprising the two contact layers 41 a, 41 b in thecontact opening 44 a forms an electrically conductive connection betweenthe selection transistors 30 a, 30 b and the trench capacitors 20 a, 20b.

[0034] In order, however, to enable each of the memory cells 15 a, 15 bto be individually charged or discharged, separation of the contactblock 40 in the contact opening 44 a is performed in a further processstep. At the same time, this produces an insulation structure 52 betweenthe two memory cells 15 a, 15 b.

[0035] As shown in FIG. 1J, for this purpose firstly an etching mask isproduced for the etching of the contact block 40 in the contact opening44 a. In this case, an insulator layer designated as spacer layer 42 isdeposited onto the contact layers 41 a, 41 b and the uncovered regionsof the insulation structures 53, running in the bit line direction, inthe spacer trench 44 b, thereby filling the interspace between theinsulation encapsulations 34 of the word lines 33 a, 33 b along the wordline direction with the spacer layer 42. The thickness of this spacerlayer 42 is configured in a manner dependent on the process and isapproximately equal to the width of the spacer trench 44 b in theexemplary embodiment illustrated. Afterward, the spacer layer 42 isetched away down to the underlying contact block 40 with the aid of ananisotropic etching method. Since the horizontal and the verticalregions of the spacer layer 42 have different rates of removal duringthe anisotropic etching, the spacer layer 42 is divided completely intotwo partial regions 42 a, 42 b, which are referred to as spacershereinafter.

[0036] The insulation opening 50 b produced in this case exhibits thefunnel-shaped etching profile illustrated in FIG. 1J, the opening 50 bin the spacer layer 42 tapering increasingly with depth, so that it hasthe smallest width in the bottommost region, directly on the contactblock 40. In the exemplary embodiment illustrated here, the insulationopening 50 b has, in the bottommost region of the spacer layer 42,approximately the width of the underlying web 11, which separates thetrench capacitors 20 a, 20 b from one another, in the semiconductorsubstrate 10. In order to ensure that the area of the memory cellarrangement is utilized as efficiently as possible, the insulationopening 50 b is generally produced such that it is as narrow aspossible. In this case, the dependence of this width on the etchingdepth is advantageously utilized, as a result of which the width of theinsulation opening 50 b can be set very precisely by means of thethickness of the deposited spacer layer 42 in the interspace between theword lines 33 a, 33 b. Thus, with the aid of this method, it is possibleto fabricate insulation openings 50 b whose width is narrower than theminimum possible lithographic web width.

[0037] In a subsequent process step, the insulation opening 50 b of thespacer layer 42 in the contact block 40 is extended right into thesemiconductor substrate 10. In this case, the spacers 42 a, 42 b, theuncovered partial regions of the insulation encapsulations 34 of theword lines 33 a, 33 b, the strip-type protective layer 14 and theinsulation structures 53, oriented in the bit line direction, in thesemiconductor layer 12 serve as etching mask, so that only the region ofthe contact block 40 which is situated below the insulation opening 50 band between the memory cells 15 a, 15 b is selectively removed with theaid of an anisotropic etching method. In this process step, as is shownin FIG. 1K, a partial region of the web 11 of the semiconductorsubstrate 10 and also partial regions of the insulation encapsulations22 of the trench capacitors 20 a, 20 b are also concomitantly removed,so that the insulation 30 opening 50 a thus produced completelyseparates the contact block 40 in the contact opening 44 a and each ofthe selection transistors 30 a, 30 b is electrically connected only tothe trench capacitor 20 a, 20 b of the respective memory cell 15 a, 15b.

[0038] In a modified embodiment, the insulation opening 50 a is formedin trench form along the entire length of the spacers 42 a, 42 b. Inthis case, in addition to the contact blocks 40, the insulationstructures 53 formed in the semiconductor layer 12 in the bit linedirection are also removed with the aid of a selective etching method toa point below the substrate surface.

[0039] In a subsequent process step, the insulation trench 50 formed bythe insulation openings 50 a, 50 b is filled with a further insulator51, as a result of which the two memory cells 15 a, 15 b areelectrically insulated from one another, as shown in FIG. 1L.

[0040]FIG. 2 shows a cross section through the semiconductor wafer withthe three memory cells 15 a, 15 b, 15 c after further process steps forthe fabrication of a bit line contact 35 a. For this purpose, a contactopening 36 down to the electrically conductive region 31 a of the twoselection transistors 30 b, 30 c is formed in the interspace between theinsulation encapsulations 34 of the word lines 33 b, 33 c. The contactopening 36 of the bit line contact 35 a is filled with an electricallyconductive material and connects the common source/drain electrode 31 aof the selection transistors 30 a, 30 b of the two memory cells 15 b, 15c to the bit line 35, which, in the exemplary embodiment illustrated, isarranged at a right angle to the word lines 33 a, 33 b, 33 c above theinsulator layer 51 b isolating the strap contacts 40 a, 40 b from thebit line 35.

[0041]FIG. 3 shows a layout of a memory cell arrangement according tothe invention with a total of 24 memory cells 15, which are arranged infour rows and six columns, three memory cells 15 of a row in each casebeing formed in a manner corresponding to the memory cells 15 a, 15 b,15 c according to FIG. 2.

[0042] In this case, the memory cells 15 have an arrangement of trenchcapacitors 20, which are illustrated by an interrupted line, andselection transistors 30, which are essentially formed above the trenchcapacitors 20 and whose gate electrodes 37 simultaneously form thecommon word line 33 of the respective column of the memory cellarrangement. The monocrystalline semiconductor layer 12 which, as isshown in FIG. 2, is formed between the trench capacitors 20 and theselection transistors 30 is subdivided in strip form in the bit linedirection by insulation trenches 53 which preferably extend right intothe semiconductor substrate. These insulation trenches 53, which runhorizontally in FIG. 3, form the field insulation in the word linedirection between the memory cells 15.

[0043] The memory cells 15 of the memory cell arrangement are situatedin the crossover regions of the word lines 33 and bit lines 35, whichare arranged perpendicularly to one another, the bit lines 35, notillustrated in FIG. 3 for the sake of clarity, running horizontally andthe word lines 33 running vertically.

[0044] As shown in FIG. 3, memory cells 15 arranged in a row of thememory cell arrangement alternately have in their interspaces a commonbit line contact 35 a and a strap contact-trench insulation arrangementaccording to the invention. The interspace between the word lines 33, inwhich a bit line contact 35 a is formed, is preferably smaller than thedouble strap contact-trench insulation arrangement according to theinvention, so that the word lines 33, as shown in FIG. 3, are arrangedoffset with respect to one another in pairs. Each bit line contact 35 acomprises a conductive layer which is formed in a contact opening 36between the word lines 33 of two memory cells 15, and contact-connectsthe electrically conductive regions 31 a of the respective selectiontransistors 30.

[0045] The strap contact-trench insulation arrangements according to theinvention are formed in the wider interspaces of the word lines 33 ineach case between two memory cells 15. For this purpose, between thememory cells 15 which are adjacent in the bit line direction, a contactopening 44 a is in each case formed in the semiconductor layer 12, whichis bounded by the insulation structures 53 in the word line direction,the contact opening 44 a extending as far as the polycrystalline trenchfilling 21 of the respective trench capacitors 20. A contact block 40 isformed within the contact opening 44 a, which contact block comprises afirst contact layer 41 a, which reaches as far as the lower level of theelectrically conductive regions 31 b in the semiconductor layer 12, anda second contact layer 41 b, which reaches as far as the upper level ofthese regions 31 b.

[0046] The central region of each contact block 40 of the memory cellarrangement is provided with an insulation opening 50 a, which is filledwith an insulator layer 51 a. In this case, the insulation opening 50 areaches to a point below the upper edge of the insulation coveringlayers 23 and is bounded by the insulation structures 53 in the wordline direction, so that the contact block 40 is separated into twomutually independent strap contacts 40 a, 40 b, which in each caseelectrically connect only the storage capacitor 20 to the selectiontransistor 30 of the respective memory cell 15. The region bounded bythe word lines 33 above the strap contacts 40 a, 40 b, the insulationopenings 50 a and the insulation structures 53 arranged in the bit linedirection has a further insulator layer. As can be seen from the crosssection in FIG. 1L and FIG. 2, this insulator layer in each casecomprises an insulator layer 51 b and two spacers 42 a, 42 b, eachspacer 42 a, 42 b being formed above the respective strap contacts 40 a,40 b along each word line 33 and the insulator layer 51 b filling theinsulation opening 50 b, separating the spacers 42 a, 42 b, to a pointabove the insulation encapsulations 34 of the word lines 33.

[0047] The insulator layer 51 a forms the field insulation structure ofthe memory cell matrix perpendicular to the bit line direction, and,together with the field insulation trenches 53 oriented in the bit linedirection, the complete insulation matrix of the memory cellarrangement.

1. A method for fabricating a memory cell arrangement having thefollowing method steps: A) formation of a trench capacitor (20) for eachmemory cell (15) in a semiconductor substrate (10) with a respectiveelectrically conductive trench filling (21); B) production of asemiconductor layer (12) above the trench capacitors (20); and C)formation of a selection transistor (30) for each memory cell (15) within each case two electrically conductive regions (31 a, 31 b) in thesurface of the semiconductor layer (12), a channel region (32) in thesemiconductor layer (12) between the two electrically conductive regions(31 a, 31 b) and an electrically conductive layer (37) on thesemiconductor layer (12), which electrically conductive layer issituated above the channel region (32) and is insulated from the latterand also from the electrically conductive regions (31 a, 31 b) andserves as a word line (33) for the respective memory cell (15);characterized by D) formation of a respective contact opening (44 a) inthe semiconductor layer (12) in the region between two adjacent memorycells (15), each contact opening (44 a) uncovering in each case a partof the electrically conductive trench filling (21) of the two associatedtrench capacitors (20) and in each case an electrically conductiveregion (31 b)—associated with the respective selection transistor(30)—in the semiconductor layer (12); E) filling of the contact opening(44 a) with an electrically conductive layer (41 a), F) formation of aninsulation opening (50 a) in the contact opening (44 a) at least as faras the upper edge of the trench capacitor (20), so that the electricallyconductive layer (41 a) in the contact opening (44 a) is divided intotwo partial regions (40 a, 40 b), each of the two partial regions (40 a,40 b) connecting the electrically conductive trench filling (21) of atrench capacitor (20) to the electrically conductive region (31 b) ofthe associated selection transistor (30); and G) filling of theinsulation opening (50 a) with an insulator layer (51), so that the twopartial regions (40 a, 40 b) of the electrically conductive layer (41 a)in the contact opening (44 a) are electrically insulated from oneanother.
 2. The method as claimed in claim 1, wherein, in method stepE), for forming the insulation opening (50 a) a further insulator layer(42) is applied above the electrically conductive layer (41 a) in thecontact opening (44 a) and is subdivided into two partial regions (42 a,42 b) by means of an anisotropic etching step without any masks, sothat, on the underlying electrically conductive layer (41 a), the regionfor the insulation opening (50 a) is uncovered and is subsequentlyremoved by means of an anisotropic etching step to a point below theupper edge of the trench capacitor (20), the partial regions (42 a, 42b) of the insulator layer (42) being constituent parts of the etchingmasking used in this process step.
 3. The method as claimed in claim 1or 2, wherein the filling of the insulation opening (50 a) with theinsulator layer (51) in method step G) is effected in such a way thatthe interspace of the word lines (33) or the insulation opening (50 b)between the two partial regions (42 a, 42 b) of the insulator layer (42)is concomitantly filled.
 4. The method as claimed in one of claims 1 to3, wherein, before the filling of the contact opening (44 a) with theelectrically conductive layer (41 a) in method step E), a preferablythin insulator layer (43) is produced on the sidewalls of the contactopening (44 a), a first electrically conductive layer (41 a) is thenformed in the contact opening (44 a) up to a height which essentiallycorresponds to the depth of the electrically conductive regions (31 b)in the semiconductor layer (12), the thin insulator layer (43) on thesidewalls of the contact opening (44 a) is at least partly removed atthe electrically conductive regions (31 b) in the semiconductor layer(12), and a second electrically conductive layer (41 b) is produced onthe first electrically conductive layer (41 a) in the contact opening(44 a) at least up to a height which corresponds to the level of theelectrically conductive regions (31 b).
 5. The method as claimed inclaim 4, wherein the thin insulator layer (43) is produced by means of achemical vapor deposition method or by oxidation.
 6. The method asclaimed in one of claims 1 to 5, wherein the word lines (33) of the twomemory cells (15) have insulation encapsulations (34) which also serveas a mask for the method steps D) and E).
 7. The method as claimed inone of claims 1 to 6, wherein the memory cells (15) are formed in rowsalong the bit lines provided and, after the method step B), insulationtrenches (53) are produced in the semiconductor layer (12) in each casebetween two adjacent rows of memory cells (15), which trenches arefilled with an insulator layer and preferably serve as a mask for one ormore of the method steps 1D) to 1G).
 8. A memory cell arrangement on asemiconductor wafer having a multiplicity of memory cells (15) arrangedin a matrix form, which each have a trench capacitor (20), formed in thesemiconductor substrate (10), with an electrically conductive trenchfilling (21) and a selection transistor (30) formed above the trenchcapacitor (20) in the surface of a semiconductor layer (12) arranged onthe semiconductor substrate (10), the selection transistor (30) beingformed by two electrically conductive regions (31 a, 31 b) formed in thesemiconductor layer (12), a channel region (32), which separates the twoelectrically conductive regions (31 a, 31 b) and is formed essentiallyabove the trench capacitor (20), and an electrically conductive layer(37), which is insulated from the electrically conductive regions (31 a,31 b) and the channel region (32) and is embodied on the semiconductorlayer (12) above the channel region (32), and a multiplicity ofessentially parallel bit lines (35) and essentially parallel word lines(33), in which case the word lines (33) are arranged perpendicularly tothe bit lines (35) and the memory cells (15) are arranged in each caseat the crossover points between the bit lines (35) and word lines (33),in which case, for in each case three memory cells (15 a, 15 b, 15 c)which are arranged along a bit line (35) and are contact-connected by arespective word line (33 a, 33 b, 33 c) at the electrically conductivelayer (37), the bit line (35), in the region between the central wordline (33 b) and one adjacent word line (33 c), contact-connects oneelectrically conductive region (31 a) of the selection transistors (30b, 30 c) of the memory cells (15 b, 15 c) assigned to the two word lines(33 b, 33 c) and a contact block (40) is formed in the semiconductorlayer (12) in the region between the central word line (33 b) and theother adjacent word line (33 a) below the bit line (35), in a mannerelectrically isolated from the latter by means of a second insulatorlayer (51 b), in which case the contact block (40) in each case with alaterally arranged, electrically conductive layer (40 a, 40 b),contact-connects the trench filling (21) of the trench capacitor (20 a,20 b) with the other electrically conductive region (31 b) of theselection transistor (30 a, 30 b) of the memory cells (15 a, 15 b)assigned to the two word lines (33 a, 33 b), in which case the twolaterally arranged electrically conductive layers (40 a, 40 b) in thecontact opening (44 a) are electrically insulated from one another by afirst insulator layer (51 a) formed in between, which extends into thesemiconductor substrate (10) right into the region between the trenchcapacitors (20 a, 20 b) and whose width essentially corresponds to thedistance between the trench capacitors (20 a, 20 b).
 9. The memory cellarrangement as claimed in claim 8, wherein a spacer insulation layer (42a, 42 b) is in each case formed above the laterally arrangedelectrically conductive layers (40 a, 40 b) of the contact block (40) inthe region between the word lines (33 a, 33 b) of the memory cells (15a, 15 b).
 10. The memory cell arrangement as claimed in either of claims8 and 9, wherein the first insulator layer (51 a) and the secondinsulator layer (51 b) are embodied as a continuous layer (51).
 11. Thememory cell arrangement as claimed in one of claims 8 to 10, wherein athin insulator layer (43) is formed between the laterally formedelectrically conductive layers (40 a, 40 b) of the contact block (40)and the semiconductor layer (12) below the electrically conductiveregions (31 b) in the semiconductor layer (12).